1. Field of the Invention
The present invention relates to a method of accessing memory locations on a network device and more particularly to a method for accessing memory locations based on a class of service associated with packets transmitted through the network device.
2. Description of the Related Art
A switching system may include one or more network devices, such as a switching chip, each of which includes several modules that are used to process information that is transmitted through the device. Specifically, the device includes an ingress module, a Memory Management Unit (MMU) and an egress module. The ingress module includes switching functionality for determining to which destination port a packet should be directed. The MMU is used for storing packet information and performing resource checks. The egress module is used for performing packet modification and for transmitting the packet to at least one appropriate destination port. One of the ports on the device may be a CPU port that enables the device to send and receive information to and from external switching/routing control entities or CPUs.
As packets enter the device from multiple ports, they are forwarded to the ingress module where switching is performed on the packets. Thereafter, the packets are transmitted to the MMU for distinguishing a Class of Service (COS) to which each packet belongs. According to one design, there are eight classes. As such, the MMU may send each packet to one of eight logical areas. After performing resource checks on the packets, the packets are transmitted to the egress module for further processing and modification. Thereafter, the egress module transmits the packets to at least one destination port, possibly including a CPU port. If the packets are being transmitted to the CPU port, the egress module forwards them through a CMIC module which sorts the packets based on the COS associated with each packet.
When packets enter the CMIC module, they are recognized to be of different priorities. For example, some packets may be recognized to be of a higher priority and others may be recognized to be of a lower priority. Thereafter, the CMIC module transmits the packets to buffers on the CPU via a PCI bus. Prior to transmitting the packets to the CPU buffers, the CMIC module pre-fetches the required packets from the MMU. So if the CPU buffer has, for example 10 slots, the CMIC module pre-fetches each of packets 1-10 and transmits them to the CPU buffer. By the time the CMIC module sends the 10th packet to the CPU buffer, the MMU may already be transmitting the 11th packet to the CMIC module to maximize the performance of the device. However, since the CPU buffer only has 10 slots, the CMIC module has no where to transmit the 11th packet until software in the CPU clears the buffer and requests additional packets. Hence, the CMIC module is stalled until the software processes the 10 packets that are already in the CPU buffer.
In some current devices, a bit may be set to either drop or block packets that are stalled in the CMIC module. If the bit is set to drop packets, the CMIC module drops all packets that are stalled, whether or not those packets are recognized to be of a higher priority or a lower priority. If the bit is set to block packets, packets that are recognized to be of lower priority may block higher priority packets and higher priority packets may block lower priority packets. In the situation described above, lower priority packets may be transferred to the CPU buffer while higher priority packets are stalled in the CMIC module. As such, the CMIC may drop higher priority packets while allowing lower priority packets to be forwarded to the CPU.